1. Field of the Invention
The present invention relates to a static semiconductor storage device (hereinafter referred to as SRAM) using field-shield isolation.
2. Description of Related Art
In general, an SRAM memory cell is constituted of six transistors. FIG. 13 is an equivalent circuit diagram of an SRAM memory cell. In FIG. 13, reference symbols 1a and 1b denote access transistors each being an n-type transistor; 2a and 2b, driver transistors each being an n-type transistor; 3a and 3b, load transistors each being a p-type transistor; 4a and 4b, bit lines; and 5, a word line. In the memory cell, the driver transistors 2a and 2b and the load transistors 3a and 3b form a flip-flop circuit.
FIGS. 14 and 15 show patterns of a related SRAM memory cell in which polysilicon interconnections in one level and metal interconnections in two levels and field-shield isolation plates are used on an SOI (silicon on insulator) substrate. Specifically, FIG. 14 shows a pattern of field-shield isolation plates, active regions, polysilicon interconnections, first-level metal interconnections, and first contact portions that connect the first-level metal interconnections to the polysilicon interconnections or the active regions. FIG. 15 shows a pattern of the field-shield isolation plates, the active regions, the polysilicon interconnections, second-level metal interconnections, and second contact portions that connect the second-level metal interconnections to the active regions or the field-shield isolation plates. The term xe2x80x9cfield-shield isolationxe2x80x9d as used in this specification means, in simple terms, device isolation that utilizes off-states of MOS transistors having a high threshold voltage. The term xe2x80x9cfield-shield isolation platexe2x80x9d corresponds to the gate of an ordinary transistor. In the following description, the field-shield isolation will be explained in a case where it is effected by field-shield isolation plates.
To reduce the resistivity of active regions on an SOI substrate, usually the surface portions of the active regions are converted to a refractory metal silicide.
In the related SRAM memory cell pattern of FIG. 14, 11a-11c denote field-shield isolation plates for n-type transistors; 11d, a field-shield isolation plate for p-type transistors; 12a-12f, n-type active regions; 12g-12j, p-type active regions; 12x-12z, active regions that are not clearly judged to be of an n-type or of a p-type; and 13a-13c, polysilicon interconnections or interconnections having a laminated structure of polysilicon and a silicide (hereinafter represented by polysilicon interconnections). Reference symbols 14a-14c denote first-level metal interconnections, and 15a-15h denote first contact portions that connect the first-level metal interconnections to the active regions or the polysilicon interconnections.
In FIG. 15, reference symbols 16a-16d denote second-level metal interconnections, and 17a-17f denote second contact portions that connect the second-level metal interconnections to the active regions or the field-shield isolation plates.
Next, the components shown in the equivalent circuit diagram of FIG. 13 will be correlated with the parts shown in FIGS. 14 and 15. As for the access transistors, for the sake of convenience, the active regions connected to the bit lines will be called drain active regions and the active regions connected to the driver transistors will be called source active regions. First, as for the transistors, the drain active region, the gate, and the source active region of the access transistor 1a are the parts 12a, 13a, and 12b, respectively; those of the access transistor 1b are the parts 12d, 13a, and 12e, respectively; those of the driver transistor 2a are the parts 12b, 13b, and 12c, respectively; those of the driver transistor 2b are the parts 12e, 13c, and 12f; those of the load transistor 3a are the parts 12g, 13b, and 12h; and those of the load transistor 3b are the parts 12i, 13c, and 12j. The bit line 4a corresponds to the part 16a, the bit line 4b corresponds to the part 16b, and the word line 5 corresponds to the part 13a. The part 14c in FIG. 14 corresponds to the Vcc interconnection and the parts 16c and 16d in FIG. 15 correspond to the GND interconnection.
FIG. 16 is a sectional view taken along line Ixe2x80x94I in FIGS. 14 and 15. In FIG. 16, reference symbols 21-23 denote a silicon portion, an insulating layer, and an interlayer insulating film, respectively.
The above-described SRAM formed on the SOI substrate by using the field-shield isolation have the following three problems.
The first problem is data destruction at storage nodes that occurs being influenced by floating potential regions. In FIG. 14, although the active regions 12x-12z are divided from each other by the field-shield isolation plates 11b and 11d and the polysilicon interconnections 13b and 13c, their potentials are not fixed. Therefore, the active regions 12x-12z are rendered in a floating potential state and influence the active regions 12b, 12e, 12g, and 12i as storage node portions in memory cell operation, and possibly cause data destruction through noise, latch-up, or the like.
The second problem is a large memory cell size. As shown in FIG. 14, the potentials of the field-shield isolation plate 11b for n-type transistors and the field-shield isolation plate 11d for p-type transistors are fixed at the GND potential and the Vcc potential, respectively. Therefore, intervals are needed between the n-type transistors and the p-type transistors. Specifically, if each of a minimum field-shield isolation width (or a minimum polysilicon interconnection width) and a minimum isolation interval (or a minimum polysilicon interval) is W, it is desirable that an interval X between the same storage nodes (see FIG. 14) be equal to 3W. However, actually, since the active regions 12x-12z between the n-type transistors and the p-type transistors are electrically unstable (the first problem mentioned above), there may occur latch-up or the like. For this reason, to make the memory cell less prone to data destruction, the interval X between the same storage nodes is set at a large value 3W+xcex1. This necessarily increases the memory cell size.
The third problem is severe hole forming conditions of the second contact portions. FIG. 17 shows a pattern of field-shield isolation plates in a case where related memory cells 40 as shown in FIGS. 14 and 15 are arranged in a 4xc3x974 (vertical/horizontal) array. Where the field-shield isolation plates 11b and 11d are arranged in array form, they assume a continuous pattern and hence the plate potentials can be fixed at ends of the array.
On the other hand, where the field-shield isolation plates 11a and 11c are solitary patterns, the plate potentials need to be fixed at the respective positions. As shown in FIG. 15, it is necessary to fix the potentials by connecting the field-shield isolation plates 11a and 11c to the second-level metal interconnections 16d and 16c via the second contact portions 17d and 17c, respectively.
Therefore, as shown in FIG. 15, it is necessary to form, in the memory cell, two kinds of second contact portions having different depths, that is, the contact portions 17a, 17b, 17e, and 17f for the active regions and the contact portions 17c and 17d for field-shield isolation plates, which leads to severe contact hole opening conditions.
The present invention has been made to solve the above problems in the art, and a first object of the invention is therefore to eliminate floating potential active regions.
A second object of the invention is to reduce the memory cell size.
A third object of the invention is to realize a memory cell configuration in which second contact portions have only one kind of depth.
According to a first aspect of the present invention, there is provided a semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a second load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a first access transistor connected to a drain active region of the first driver transistor and a drain active region of the first load transistor; and a second access transistor connected to a drain active region of the second driver transistor and a drain active region of the second load transistor, wherein device isolation in the memory cell includes field-shield isolation, and isolation between active regions of the first driver transistor and active regions of the first load transistor and isolation between active regions of the second driver transistor and active regions of the second load transistor are effected by oxide film isolation.
According to a second aspect of the present invention, there is provided a semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a second load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a first access transistor connected to a drain active region of the first driver transistor and a drain active region of the first load transistor; and a second access transistor connected to a drain active region of the second driver transistor and a drain active region of the second load transistor, wherein device isolation in the memory cell includes field-shield isolation, and at least part of isolation regions that are in contact with the drain active regions of the first and the second driver transistors and the drain active regions of the first and the second load transistors are isolated by oxide film isolation.
According to a third aspect of the present invention, there is provided a semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a second load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a first access transistor connected to a drain active region of the first driver transistor and a drain active region of the first load transistor; and a second access transistor connected to a drain active region of the second driver transistor and a drain active region of the second load transistor, wherein device isolation in the memory cell includes field-shield isolation, active regions of the first access transistor and the drain active region of the first driver transistor are isolated from each other by field-shield isolation and connected to each other via a metal interconnection, and active regions of the second access transistor and the drain active region of the second driver transistor are isolated from each other by field-shield isolation and connected to each other via a metal interconnection.
According to a fourth aspect of the present invention, there is provided a semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a second load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a first access transistor connected to a drain active region of the first driver transistor and a drain active region of the first load transistor; and a second access transistor connected to a drain active region of the second driver transistor and a drain active region of the second load transistor, wherein device isolation in the memory cell includes field-shield isolation, first and second active regions of the first access transistor and active regions of the second access transistor are arranged substantially on a straight line, and a word line that is connected to the first and the second access transistors is formed on a portion of a field-shield isolation plate that is located between the first active region of the first access transistor and a source active region of the first driver transistor.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.